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ATmega128
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
? Bit 3 – CPOL: Clock Polarity
W hen this bit is written to one, SCK is high when idle. W hen CPOL is written to zero, SCK is low
when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summa-
rized below:
Table 70. CPOL functionality
CPOL
0
1
Leading edge
Rising
Falling
Trailing edge
Falling
Rising
? Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example. The CPHA func-
tionality is summarized below:
Table 71. CPHA functionality
CPHA
0
1
Leading edge
Sample
Setup
Trailing edge
Setup
Sample
? Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f osc is
shown in the following table:
Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f osc / 4
f osc / 16
f osc / 64
f osc / 128
f osc / 2
f osc / 8
f osc / 32
f osc / 64
167
2467X–AVR–06/11
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